Electrochemical processing of oxides on metals and semiconductors is well-known in the art of passive oxide formation and electroetching. Formation of a passive native oxide on a substrate tends to be self-limiting, since the process stops when the electrochemically formed oxide is thick enough to prevent current flow. By correct control of the process conditions, good coatings can be obtained. In this regard, see, for example, U.S. Published Application No. 2002/0104761 A1, to Birss et al., the entire disclosure of which is incorporated herein by reference.
The formation of reliable SiO2 gate oxides on p-type Si by a combination of electrochemical anodization and conventional oxide formation techniques has been shown by W-J. Lia et. al., in J. Electrochem. Soc. 151 (9) G549-G553 (2004), the entire disclosure of which is incorporated herein by reference Rare-earth oxides have been directly deposited onto a substrate from organic as well as aqueous electrolytes containing salts of a rare earth metal. For example Y. Matsuda et al. have electrodeposited Y2O3 and Y2O3:Eu(III) on conductive SnO2 substrates using dimethylformide (DMF) with added YCl3 and EuCl3 salts, as described in the Journal of Alloys and Compounds, 193, 277-279 (1993), the entire disclosure of which is incorporated herein by reference. In addition, M. A. Petit et al. have electrodeposited conductive iridium oxide films on SnO2 substrates from an aqueous solution of K3IrC6, oxalic acid and potassium carbonate, as described in Electroanal. Chem. 444, 247-252 (1998), the entire disclosure of which is incorporated herein by reference.
A prior art approach to electrochemical modification of gate oxides is described in U.S. Pat. No. 6,352,939 to Hwu et. al., the entire disclosure of which is incorporated herein by reference. In this approach, a low-level current (0.1-10 μA/cm2) is passed through gate a dielectric in a Si(substrate)/gate oxide/electrolyte structure towards a metal plate in an aqueous electrolyte solution. The disruption to the bonds throughout the thickness of the dielectric is then repaired by a post-treatment anneal. Improved dielectric properties were reported for Sio2, Si3N4 and Ta2O5. However, no chemical modifications (i.e., introduction of new elements not already in the dielectric) would be expected with, the non-reactive solution chemistry employed (dilute aqueous HF), and the treatment is directed toward modifying the bulk of the dielectric; rather than its surface.
In the art of electrodeposition for semiconductor manufacturing and for fabrication of metal structures on dielectrics, the electro deposited metal is nearly always deposited on a metallic seed or plating base layer formed on a substrate by a method other than electrodeposition e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), etc.). The main path for the current flow driving the electrodeposition is laterally through the seed layer, from contact established at the seed layer edges. Current through the substrate itself, and any dielectric layers contained therein, is typically completely negligible. Plating can be limited to selected areas of the seed layer by using though-mask plating techniques, wherein one plates through the openings in an insulating masking layer disposed directly on the seed layer.
High performance CMOS devices can be expected to increasingly incorporate, high-k gate dielectrics and metal gates. In the fabrication of metal gates, the conventional approach has been subtractive, i.e., the metal gate material is applied as a blanket layer and then selectively removed from regions where it is not wanted. The above electrodeposition approach has been described as an additive method, for forming metal gates for field effect transistors in U.S. patent application Ser. No. 10/694,793 entitled “Field Effect Transistor with Electroplated Metal Gate,” the entire disclosure of which is incorporated herein by reference. The gate metal may be selectively deposited on the desired gate regions by through-mask plating onto a blanket conductive seed layer, which would typically be removed from the masked regions after the plating process. This prior art further discloses that the gates for n-FET and p-FET devices have different work functions and comprise different metals, which means that the additive through-mask plating approach must be done more than once.
It would therefore be desirable to provide a method of plating a gate metal directly onto a gate dielectric without the need for a seed layer. It would also be desirable to have a through-mask plating method which could selectively plate a first material in a first subset of mask openings and then selectively plate a second material into a second subset of mask openings, where the first and second subsets of mask openings differ in the doping of the semiconductor material under the gate dielectric. In addition, it would be desirable to have a method of gate dielectric interface engineering, whereby the properties of the gate material can be altered or fine-tuned by surface modification.